Phase lock loops (PLLs) and clock recovery circuits (CRCs) have found wide application in such diverse areas as digital communication systems, wireless systems, digital circuits and data recovery systems for use in connection with mass storage media such as hard disk, tape and optical drives. In the field of digital communication systems, phase lock loops are typically used in modern digital communications receivers to recover useful data from a transmission signal stream by providing data recovery circuitry with a timing reference having the appropriate frequency and phase characteristics so as to match timing characteristics of the transmitted signal and thus, ensure proper data recovery.
In modern HDTV signal transmissions, a receiver must be capable of locking onto a transmitter's pilot carrier phase as well as the transmitter's timing phase. Locking the receiver to the transmitter's carrier phase is commonly referred to as carrier phase recovery, whereas locking onto the timing phase of the transmitter is referred to as timing phase recovery. Both of these functions are critical to a modern day communications system since the receiver must be synchronized to the transmitter in order that transmitted data may be correctly demodulated, and equalized.
Applications of phase lock loops (or more correctly frequency-phase locked loops, FPLLS) in a modern high-speed communications system would include their use as frequency acquisition tools in a receiver's channel tuner and as an automatic gain control (AGC) loop, disposed within a channel tuner, which ensures that the power level of a received signal is suitably limited to a particular desired level. Thus, it can be seen that PLLs and FPLLs play a significant role in the effective operation of various portions of a modern digital communication system. Indeed, it is difficult to conceive of a modern high-speed digital communications system that does not make extensive use of precision PLLS.
Notwithstanding the necessity of their use in modern communication systems, conventional PLLs suffer from a particular disadvantage that makes their use in modern, high-speed communication systems problematic. This disadvantage relates most particularly to the time characteristics of the phase error response of a first order or second order PLL in response to a prompt change in the phase of an input signal. Given the extremely precise phase and timing alignments required in modern high-speed communication systems, and their correspondingly small phase error margins, a false designation of phase lock during a phase acquisition procedure can very easily result in the loss of system timing and a consequent disruption of, for example, carrier recovery operations and thus, a loss of signal.